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ทำไมคอมไพล์ไม่ผ่านครับ

ผมเขียนโปรแกรม VHDL ดังนี้มัน error ครับ บอกว่า Signal "Tx_en" has multiples sources และ Signal "Serial_OUT" has multiples sources ครับ เป็นเพราะไร?? ผมใช้ std_ulogic แล้วนี่นา (โปรแกรม max+plus2)ครับ

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Core1 IS
PORT(
Clk, Key_tig ,Rx_en : IN STD_LOGIC;
Serial_IN : IN STD_LOGIC_VECTOR(7 downto 0);
Key_Data : IN STD_LOGIC_VECTOR(7 downto 0);
Off_line, On_line, Tx_en : OUT STD_LOGIC;
Serial_OUT : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END Core1;

ARCHITECTURE rtl OF Core1 IS
TYPE Stat1 IS (Online, Offline);
SIGNAL Status : Stat1;
BEGIN
PROCESS(Clk,Rx_en) -- Wait for 'R' every clock cycle and let status = 'Online' if so
BEGIN
IF Clk'EVENT and Clk ='1' THEN
IF Rx_en = '1' THEN
IF Serial_IN = "01010010" THEN -- Check if Serial_IN = 'R' or 'r'
Status <= Online;
On_line <= '1';
Off_line <= '0';
ELSE
Status <= Offline;
On_line <= '0';
Off_line <= '1';
END IF;
END IF;
END IF;
END PROCESS;

PROCESS(Clk,Status) -- Send 'A' every 1 second if 'Offline' status
VARIABLE Count : integer range 0 to 9600 := 0;
BEGIN
IF Clk'EVENT and Clk = '1' THEN
IF Status = Offline THEN
IF Count < 9599 THEN
Count := Count + 1;
Tx_en <= '0';
ELSE
Count := 0;
Serial_OUT <= "01000001";
Tx_en <= '1';
END IF;
END IF;
END IF;
END PROCESS;

PROCESS(Clk,Status) -- Send Enable Signal (Tx_en) form keyboard
BEGIN
IF Clk'EVENT and CLK = '1' THEN
IF Status = Online THEN
Serial_OUT <= Key_Data;
Tx_en <= Key_tig;
END IF;
END IF;
END PROCESS;
END rtl;